This paper describes the architecture and operating principles of two digital pulse-width modulator (DPWM) implementations for low-cost field-programmable gate arrays (FPGAs). The technique is evaluated using a case study of parallel finite impulse response filters showing the effectiveness in terms of protection and implementation cost. This new scheme allows more efficient protection when the number of parallel filters is large. In this brief, that idea is generalized to show that parallel filters can be protected using error correction codes (ECCs) in which each filter is the equivalent of a bit in a traditional ECC.
Recently, a simple technique that exploits the presence of parallel filters to achieve fault tolerance has been presented. In those complex systems, it is common that some of the filters operate in parallel, for example, by applying the same filter to different input signals. As technology scales, it enables more complex systems that incorporate many filters. Over the years, many techniques that exploit the filters’ structure and properties to achieve fault tolerance have been proposed. In some cases, the reliability of those systems is critical, and fault tolerant filter implementations are needed. Digital filters are widely used in signal processing and communication systems.
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